AFBR-703SDZ & AFCT-701SDZ Overview

The Avago AFBR-703SDZ transceiver is part of its SFP+ SR product family. This transceiver uses Avago’s 850 nm VCSEL and PIN detector technology to provide an IEEE 10 Gbs Ethernet design compliant with the 10 GBASE-SR standard. The AFBR-703SDZ transceiver is designed to enable 10 Gbs Ethernet equipment designs with very high port density based on the new electrical and mechanical specification enhancements to the well known SFP+ specifications developed by the SFF Committee.

The Avago AFCT-701SDZ transceiver is part of its SFP+ LR product family. This transceiver uses Avago’s 1310 nm DFB and PIN detector technology to provide an IEEE 10 Gbs Ethernet design compliant with the 10 GBASE-LR standard. The AFCT-701SDZ transceiver is designed with an extended case temperature to 0-85° C to enable 10 Gbs Ethernet equipment designs with very high port density based on the new electrical and mechanical specification enhancements to the well known SFP+ specifications developed by the SFF Committee.

Xilinx Product: Virtex-6 HXT FPGA Optimized for applications that require ultra-high speed serial connectivity, offer the industry’s highest serial bandwidth through a combination of 6.6 Gbps GTX transceivers and 11.18 Gbps GTH transceivers to enable next-generation packet and transport, switch fabric, video switching, and imaging equipment. The Virtex-6 FPGA Providing higher performance and lower power consumption compared to competitive FPGA offerings, the new devices operate on a 1.0 V core voltage with an available 0.9 V low-power option.

Transmitter Optical and Electrical Performance Test

Measurement Setup

The setup for transmitter optical and electrical performance measurement is shown in Figure 1 and Figure 2. The PRBS encoded 10.3125 Gbps signal generated by the Virtex FPGA was used for these measurements. An Anritsu clock generator running at 2.5776 GHz was used to trigger the Agilent DCAJ while a 161.1 MHz signal (data rate divided by 64) was used as the reference clock input to the Virtex FPGA. The measurements were taken for normal and stressed conditions using the following fiber optic links:

1. Unstressed testing: 1 m long LC fiber patch cable
2. Stressed testing: 300 m multimode OM3 fiber for SFP+ SR and 10 km single mode fiber for SFP+ LR parts.

Virtex-6 FPGA settings:

• Loopback Mode: None Pre-emphasis: 1
• Post-emphasis: 10
• Rx Equalizer: 5.67 dB Virtex DFE set: Adaptive
• Pattern used for jitter measurement: PRBS-15
• Pattern used for mask margin and BER
• measurement: PRBS-31

Figure 2. SFP+ SR and LR Interop measurement setup

AFBR-703SDZ SFP+ SR Rx Stressed Sensitivity using 300 m OM3 Fiber

Measurement Setup

The Rx stressed sensitivity measurement setup is shown in Figure 3. The PRBS encoded 10.3125Gbps signal generated by the Virtex FPGA was used for this measurement. An Anritsu clock generator running at 2.5776 GHz was used to trigger the Agilent DCA-J while a 161.1 MHz signal (data rate divided by 64) was used as the reference clock input to the Virtex FPGA. The measurements were taken using 300 m multimode OM3 for SR parts.

The Rx stressed sensitivity for five SR parts are plotted in Figure 4. The maximum measured Rx Sensitivity under this condition is -14 dBm OMA. This provides 6.5 dB of margin when compared with the IEEE802.3ae specified value of 7.5 dBm OMA for stressed Rx sen-sitivity (SRS).

Virtex-6 FPGA settings:Loopback Mode: None

• Pre-emphasis: 1
• Post-emphasis: 10
• Rx Equalizer: 5.67 dB
• Virtex DFE set: Adaptive
• Pattern used for mask margin and BER measurement: PRBS-31

AFCT-701SDZ SFP+ LR Rx Stressed Sensitivity using 10km Fiber

Measurement Setup

The setup for Rx stressed sensitivity measurement is shown in Figure 3. The PRBS encoded 10.3125 Gbps signal generated by the Virtex FPGA was used for this measurement. An Anritsu clock generator running at 2.5776 GHz was used to trigger the Agilent DCA-J while 161.1 MHz signal (data rate divided by 64) was used as the Reference clock input to the Virtex. The measurements were taken using 10 km single mode fiber for LR parts.

The Rx stressed sensitivity for five LR parts are plotted in Figure 5. The maximum measured Rx Sensitivity under this condition is -14 dBm OMA. This provides 3.7 dB of margin when compared with the IEEE802.3ae specified value of -10.3 dB OMA for stressed Rx Sen-sitivity (SRS).

Virtex-6 FPGA settings:

• Loopback Mode: None
• Pre-emphasis: 1
• Post-emphasis: 10
• Rx Equalizer: 5.67 dB
• Virtex DFE set: Adaptive
• Pattern used BER measurement: PRBS-31

Summary

The transmit channel measurements were done with the maximum applicable optical link lengths of 300 m for SR and 10 km for LR parts. The transmit channel results display excellent margin to the standard’s required mask and industry jitter performance.

The Rx stress sensitivity measurement with the maximum applicable link lengths and Circadiant generated standard stress measurements have has also shown excellent margin to the specification.

Successful component level interoperability of the Avago Technologies 10 Gbs Ethernet SFP+ transceiver products, the AFCT-701SDZ (SFP+ LR) and the AFBR-703SDZ (SFP+ SR), with the Xilinx Virtex-6 PHY FPGA has been demonstrated.

For product information please go to our web site: www.avagotech.com